1. Field of the Invention
The present invention generally relates to high-speed inter chip optical connections and more particularly to high speed optical inter board connections between logic and/or memory chips on different printed circuits, e.g., connected to a backplane.
2. Description of the Related Art
FIG. 1 shows an example of a state of the art electro-optical assembly 100 with a passive backplane 101 connecting two circuit boards 103 each with mounted electro-optical components 105. The boards 103 pass signals to each other over the passive backplane 101 through connectors 107. Chips 108, 110, 112, 114 populate and are packaged in the optical component modules 105.
FIGS. 2A–B show an example of typical orthogonal cross sections of the general board structure 200 of either/both of the backplane and circuit boards. This passive board structure 200 includes both electrical wiring channels 203 and optical wiring channels 205. A dielectric backplane/board material 201 provides a mechanical structure for maintaining and protecting the embedded copper wiring infrastructure and power distribution on wiring channels 203. Wiring channels 203 provide electronic signal media in the X and Y dimensions with interlayer or interlevel vias (not shown) connecting electrical signals between different wiring layers.
On one surface of the backplane/board are optical wave guides 205, which are shown here in a single layer. These optical wave guides 205 can be a suitable polymer or glass material deposited on the preexisting surface of the backplane/board material, or it can be an independently manufactured structure containing polymers or glass or optical fibers, that is laminated onto the board material. A fill material 207 separates the optical wave guides. The fill 207 provides isolation and planarity.
So, from FIG. 1 typical losses in a chip-to-chip (e.g., 108–112) optical path crossing the backplane 101 can be determined. In this example, the onboard path may be 50 centimeters for each board 103, with the boards spaced apart on the backplane 101 by 1 meter. The optical material is a polymer, for example. A typical board polymer exhibits a 0.03 dB/cm loss and a typical backplane polymer exhibits a 0.05 dB/cm loss. A typical chip to board coupling loss is 3 dB and a typical board to backplane connector loss is 2 dB. Thus, for this path, the signal loss is 18 dB.
This 18 dB signal loss is substantial and, remembering that each 3 dB drop corresponds to loss of halving the signal, corresponds to a sixty four time signal reduction, i.e., the receiver signal at chip 114 is 1/64 the strength at chip 108. So, to compensate for an 18 dB loss the transmitted signal at chip 108 must have 64× the signal required at the receiver chip 114. This is an unacceptable power requirement, particularly when tens of these signals are required for a typical data path and well in excess of what is usually allowed for data communications optical paths.
There are a number of known approaches to driving down these losses. Chip-to-board coupling losses can be reduced with better electro-optical packaging. Better materials can be used to reduce Channel losses, e.g., laminating fibers into the board (instead of depositing a polymer) is a costly approach to making channel losses negligible. Finally, improved (and more expensive) connectors can reduce board-to-backplane coupling loss. Connector losses result primarily from mechanical mismatches and so, can be improved by reducing tolerances, e.g., with precision mechanical machining. Unlike material changes (e.g., in the channels), precision mechanical machining requires new and better tools and processing, which is not an incremental cost increase. Each of these three state of the art approaches produce incremental improvements only with solving difficult engineering problems accompanied by sometimes dramatic cost increases. It may be possible using some combination of these approaches to reduce the loss of the above example from 18 dB to an acceptable level, e.g., 9 dB or an 8× reduction from the transmitted signal to the receiver.
FIG. 3 shows an example of a multidrop backplane 300, e.g., in a large switch or a server backplane. There may be thousands of such signals on a typical such backplane 300. Such a multidrop backplane 300 is particularly suited for servers to bus or distribute (multidrop) the signals, i.e., to fan out each transmitted signal in parallel to numerous (e.g., 8, 16, or even 32) boards 302 connected to the backplane 300.
However, with the boards 302 connected to “tap points” along the backplane optical channels, some signal is lost at each tap point. So, if each “tap point” causes a few dB signal drop from the originally transmitted signal strength (a 3 dB drop per tap point is quite optimistic), adding 3 boards to the improved path increases the total signal loss back to 18 dB. Clearly, the added work and expense has not provided for inclusion of more than a few more boards. For thousand of signals (instead of tens of signals), the total power required is prohibitive.
Furthermore, such a 4 to 5 board system would be inflexible, unscalable beyond 5 boards. Likewise removing 1 or 2 boards for a midrange system would not scale particularly easily either. Signal integrity and radiation issues would arise in the infrastructure which is designed for the 4–5 board system.
Thus, there is a need for an assembly including a backplane with multiple boards optically connected together for use in a large switch or in a server. There is a further need for such an assembly that may be constructed from a wide range of wave guide materials and in particular, those that are tolerant of channel loss. Further, there is a need for such an assembly that is tolerant of mechanical misalignment, thereby avoiding a requirement for precise mechanical alignment (i.e., that is tolerant of large coupling loss in the board-to-backplane connectors). There is also a need for such an assembly that allows multidropping signals transmitted from one board, so that multiple boards can receive the signal. Finally, there is a need for a scalable assembly that allows for a wide range of system scaling (i.e., a few boards to many boards) on a single physical infrastructure or backplane.